James Anderson of Huntington Beach, Calif., and Gershon Akerling of Culver City, Calif., have developed a method for packaging integrated circuits in a wafer format that eliminates wire bonds.

According to the U.S. Patent & Trademark Office: "A wafer substrate on which the integrated circuits have been fabricated is patterned and etched to form signal and ground via through the substrate. A back-side ground plane is deposited in contact with the ground vias."

An abstract of the invention, released by the Patent Office, said: "A protective layer is formed on the top surface of the substrate, and a protective layer is formed on the bottom surface of the substrate, where the bottom protective layer fills in removed substrate material between the integrated circuits. Vias are formed through the bottom protective layer, and the wafer substrate is diced between the integrated circuits."

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