When creating a new IC, all of the initial focus is naturally on the design. When it comes to tape-out, then fabrication, multi-project wafer (MPW) services are growing in popularity as deep subµm technologies become the norm, and both mask and wafer fabrication costs soar. However, device packaging is often overlooked until the end of process. This may be the result of some fabs and MPW providers having relatively little to offer with respect to packaging, or it may be simply that you see it as the last thing you need to worry about.

In fact, choosing the right package both during the creation of a chip, for the test phase of development, and for the final device can shorten time-to-market and create tangible benefits for customers. The number of package choices has never been greater and some MPW providers now recognise the importance of providing chip developers with optimised packages throughout the development of silicon devices. Most frequently, this is done through partnering with established packaging specialists. Here is a look at some of the available options and what they have to offer.

Being able to carry out focused ion beam analysis and probing during development is important, and open cavity packages are ideal for such tests. These tests speed up design work and ensure device integrity before moving on to volume production. However, these packages were usually large ceramic types. These are expensive, and high-speed SI cannot be evaluated accurately because package interconnects are not the same as those that will be used in the final package.

Open cavity packages

Recent developments have changed all of that and open-cavity packages are now available in several popular formats including QFN/MLP, QFP and SOIC/SSP. These pre-moulded packages meet the latest Jedec outline and footprint standards. Their copper lead frames are gold-plated to military standards, so they are mechanically stable and have very similar electrical characteristics to fully encapsulated, moulded types that would be used in volume production. Typical package sizes are from 3mm x 3mm to 10mm x 10mm.

Chip-scale packages

Relatively low cost, small size, and high performance make chip-scale packaging (CSP) a popular choice. It provides protection for the die surface, minimises stress between the PCB and the die, and facilitates changes in interconnect arrangements between the die and PCB. High-speed signal performance is particularly good because interconnects are kept very short. Rather than the conventional process of wafer fabrication, dicing and packaging, the creation of wafer level CSP involves packaging complete wafers and then dicing them, as shown in Figure 1.

Creating a CSP involves covering the wafer with a layer of passivation (polyimide) then etching vias down to the bond pads, which are traditionally located around the outside of each device, and filling the vias with conductive material. A copper re-tracing layer is then deposited that connects to the top of the vias and forms a matrix pattern across the whole chip. Solder bumping - creating the balls that will contact the PCB - is achieved by depositing a thick layer of passivation, etching vias into this at the desired connection points, then filling the vias with solder. The top layer of passivation is then removed and surface tension makes the columns of solder form into ball shapes. The final construction is shown in Figure 2a. Highest performance is achieved by keeping critical signals on the outside of the device so that they have the shortest connections to the die. CSP also offers very good thermal performance - heat is easily dissipated because there is no insulating packaging surrounding the die.